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AT45CS1282 [Preliminary]
The six most-significant bits of the status register will contain device information, while
the remaining two least-significant bits are reserved for future use and will have unde-
fined values. After the one byte of t he status register has been clocked out, the
sequence will repeat itself (as long as CS remains low and SCK/CLK is being toggled).
The data in the status register is constantly updated, so each repeating sequence will
output new data.
Ready/busy status is indicated using bit 7 of the status register. If bit 7 is a 1, then the
device is not busy and is ready to accept the next command. If bit 7 is a 0, then the
device is in a busy state. Since the data in the status register is constantly updated, the
user must toggle SCK/CLK pin to check the ready/busy status. There are four opera-
tions that can cause the device to be in a busy state: Main Memory Page to Buffer
Transfer, Main Memory Page to Buffer Compare, Buffer to Main Memory Page Program
and Sector Erase.
The result of the most recent Main Memory Page to Buffer Compare operation is indi-
cated using bit 6 of the status register. If bit 6 is a 0, then the data in the main memory
page matches the data in the buffer. If bit 6 is a 1, then at least one bit of the data in the
main memory page does not match the data in the buffer.
The device density is indicated using bits 5, 4, 3, and 2 of the status register. For the
AT45CS1282, the four bits are 0, 1, 0, 0. The decimal value of these four binary bits
does not equate to the device density; the four bits represent a combinational code
relating to differing densities of DataFlash devices. The device density is not the same
as the density code indicated in the JEDEC device ID information. The device density is
provided only for backward compatibility.
Status Register Format
Bit 7
RDY/BUSY
Bit 6
COMP
Bit 5
0
Bit 4
1
Bit 3
0
Bit 2
0
Bit 1
X
Bit 0
X
7
3447A–DFLSH–2/04
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